Datasheet

MSCAN
Register Descriptions
MC9S12DP256 — Revision 1.1
MSCAN
MSCAN Transmit
Error Counter
Register
(CANTXERR)
This register reflects the status of the MSCAN transmit error counter.
Read: only when in Sleep Mode (SLPRQ=1 and SLPAK=1) or
Initialization Mode (INITRQ=1 and INITAK=1)
Write: unimplemented
WARNING: Reading this register when in any other mode other than sleep or
initialization, may return an incorrect value.
Writing to this register when in special modes can alter the MSCAN
functionality.
MSCAN Identifier
Acceptance
Registers
(CANIDAR0–7)
On reception, each message is written into the background receive
buffer. The CPU is only signalled to read the message if it passes the
criteria in the identifier acceptance and identifier mask registers
(accepted); otherwise, the message is overwritten by the next message
(dropped).
The acceptance registers of the MSCAN are applied on the IDR0 to
IDR3 registers (see Identifier Registers (IDR0–3)) of incoming
messages in a bit by bit manner (see Identifier Acceptance Filter).
For extended identifiers, all four acceptance and mask registers are
applied. For standard identifiers, only the first two (CANIDAR0/1,
CANIDMR0/1) are applied.
Address Offset: $000F
Bit 7 654321Bit 0
Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0
Write:
Reset: 00000000
= Unimplemented
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