Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

MSCAN
MC9S12DP256 — Revision 1.1
MSCAN
LDAA CANTFLG ; value read is 8’b0000_0110
STAA CANTBSEL ; value written is 8’b0000_0110
LDAA CANTBSEL ; value read is 8’b0000_0010
. ;
. ; Fill TxBuffer
. ;
LDAA CANTBSEL ; Read actual TxBuffer selection
STAA CANTFLG ; Transmit selected TxBuffer
NOTE:
If all transmit message buffers are deselected no accesses are allowed
to the CANTXFG registers.
MSCAN Identifier
Acceptance
Control Register
(CANIDAC)
The CANIDAC register provides for identifier acceptance control as
described below.
Read: anytime
Write: anytime in Initialization Mode (INITRQ=1 and INITAK=1), except
bits IDHITx which are unimplemented
IDAM1–IDAM0 — Identifier Acceptance Mode
The CPU sets these flags to define the identifier acceptance filter
organization (see Identifier Acceptance Filter). Table 91 summarizes
the different settings. In Filter Closed mode, no message is accepted
such that the foreground buffer is never reloaded.
Address Offset: $000B
Bit 7 654321Bit 0
Read: 0 0
IDAM1 IDAM0
0 IDHIT2 IDHIT1 IDHIT0
Write:
Reset: 00000000
= Unimplemented
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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