Datasheet

Pinout and Signal Description
Signal Descriptions
MC9S12DP256 — Revision 1.1
Pinout and Signal Description
XADDR17 PK3 VDDX 5
Expanded addresses
XADDR16 PK2 VDDX 6
XADDR15 PK1 VDDX 7
XADDR14 PK0 VDDX 8
IOC0 PT0 VDDX 9
Capture Timer Channel
IOC1 PT1 VDDX 10
IOC2 PT2 VDDX 11
IOC3 PT3 VDDX 12
VDD1 VDD1 13
2.5V core supply
VSS1 VSS1 14
IOC4 PT4 VDDX 15
Capture Timer Channel
IOC5 PT5 VDDX 16
IOC6 PT6 VDDX 17
IOC7 PT7 VDDX 18
XADDR19 PK5 VDDX 19
Expanded Addresses
XADDR18 PK4 VDDX 20
KWJ1 PJ1 VDDX 21
General Purpose I/O and Interrupt
KWJ0 PJ0 VDDX 22
MODC_TAGHI BKGD VDDR 23
Pseudo_open_drain communication pin for the
single-wire background debug mode. At the rising
edge on RESET, the state of this pin is latched into the
MODC bit to set the mode. When instruction tagging is
on, a 0 at the falling edge of E tags the high half of the
instruction word being read into the instruction queue.
ADDR0_DATA0 PB0 VDDR 24
External bus pins share function with general-purpose
I/O port B. In single chip modes, the pins can be used
for general-purpose I/O. In expanded modes, the pins
are used for the external address and data buses.
ADDR1_DATA1 PB1 VDDR 25
ADDR2_DATA2 PB2 VDDR 26
ADDR3_DATA3 PB3 VDDR 27
ADDR4_DATA4 PB4 VDDR 28
ADDR5_DATA5 PB5 VDDR 29
ADDR6_DATA6 PB6 VDDR 30
ADDR7_DATA7 PB7 VDDR 31
Table 7 MC9S12DP256 Signal Description Summary
Pin Function Pin Name
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Description
112-pin
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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