Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

MSCAN
MC9S12DP256 — Revision 1.1
MSCAN
TSTATE1, TSTATE0 — Transmitter Status Change Enable
These TSTAT enable bits control the sensitivity level in which
transmitter state changes are causing CSCIF interrupts. Independent
of the chosen sensitivity level the TSTAT flags still indicate the actual
transmitter state and are only updated if no CSCIF interrupt is
pending.
11 = generate CSCIF interrupt on all state changes
10 = generate CSCIF interrupt only if the transmitter enters or
leaves ‘TxErr’ or ‘BusOff’ state. Discard other transmitter state
changes for generating CSCIF interrupt.
01 = generate CSCIF interrupt only if the transmitter enters or
leaves ‘BusOff’ state. Discard other transmitter state changes
for generating CSCIF interrupt.
00 = do not generate any CSCIF interrupt caused by transmitter
state changes.
OVRIE — Overrun Interrupt Enable
1 = An overrun event causes an error interrupt request.
0 = No interrupt request is generated from this event.
RXFIE — Receiver Full Interrupt Enable
1 = A receive buffer full (successful message reception) event
causes a receiver interrupt request.
0 = No interrupt request is generated from this event.
MSCAN
Transmitter Flag
Register
(CANTFLG)
The Transmit Buffer Empty flags each have an associated interrupt
enable bit in the CANTIER register.
Address Offset: $0006
Bit 7 654321Bit 0
Read: 0 0 0 00
TXE2 TXE1 TXE0
Write:
Reset: 00000111
= Unimplemented
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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