Datasheet

MSCAN
MC9S12DP256 — Revision 1.1
MSCAN
RXF — Receive Buffer Full
The RXF flag is set by the MSCAN when a new message is available
in the receiver FIFO. This flag indicates whether the shifted buffer is
loaded with a correctly received message (matching identifier,
matching Cyclic Redundancy Code (CRC) and no other errors
detected). After the CPU has read that message from the RxFG buffer
in the receiver FIFO, the RXF flag must be cleared to release the
buffer. Depending on the clocking relationship between CAN and
CPU clock domain the time until the RXF flag gets asserted again will
vary
1
. A set RXF flag prohibits the shifting of the next FIFO entry into
the foreground buffer (RxFG). If not masked, a Receive interrupt is
pending while this flag is set.
1 = The receiver FIFO is not empty. A new message is available in
the RxFG.
0 = No new message available within the RxFG.
WARNING: To ensure data integrity, do not read the receive buffer registers
while the RXF flag is cleared.
MSCAN Receiver
Interrupt Enable
Register
(CANRIER)
This register contains the interrupt enable bits for the interrupt flags
described above.
NOTE: The CANRIER register is held in the reset state
2
when the Initialization
Mode is active (INITRQ=1 and INITAK=1). This register is writable again
as soon as the Initialization Mode is left (INITRQ=0 and INITAK=0).
1. In case there is another CAN message in the FIFO buffer.
Address Offset: $0005
Bit 7 654321Bit 0
Read:
WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE
Write:
Reset: 00000000
2. The RSTATE[1:0], TSTATE[1:0] bits are not affected by Initialization Mode
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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