Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

MSCAN
Register Descriptions
MC9S12DP256 — Revision 1.1
MSCAN
blocking interrupt. That guarantees that the Receiver / Transmitter
status bits (RSTAT/TSTAT) are only updated when no CAN Status
Change interrupt is pending. If the TECs/RECs change their current
value after the CSCIF is asserted and therefore would cause an
additional state change in the RSTAT/TSTAT bits, these bits keep
their old state bits until the current CSCIF interrupt is cleared again.
1 = MSCAN changed current bus status.
0 = No change in bus status occurred since last interrupt.
RSTAT1–RSTAT0 — Receiver Status Bits
The values of the Error Counters control the actual bus status of the
MSCAN. As soon as the Status Change Interrupt Flag (CSCIF) is set
these bits indicate the appropriate receiver related bus status of the
MSCAN. The coding for the bits RSTAT1, RSTAT0 is:
11 = BusOff
1
: 255 > Transmit Error Counter
10 = RxERR: 127 < Receive Error Counter
01 = RxWRN: 96 < Receive Error Counter ≤ 127
00 = RxOK: 0 ≤ Receive Error Counter ≤ 96
TSTAT1–TSTAT0 — Transmitter Status Bits
The values of the Error Counters control the actual bus status of the
MSCAN. As soon as the Status Change Interrupt Flag (CSCIF) is set
these bits indicate the appropriate transmitter related bus status of the
MSCAN. The coding for the bits TSTAT1, TSTAT0 is:
11 = BusOff: 255 > Transmit Error Counter
10 = TxERR: 127 < Transmit Error Counter ≤ 255
01 = TxWRN: 96 < Transmit Error Counter ≤ 127
00 = TxOK: 0 ≤ Transmit Error Counter ≤ 96
OVRIF — Overrun Interrupt Flag
This flag is set when a data overrun condition occurs. If not masked,
an Error interrupt is pending while this flag is set.
1 = A data overrun detected.
0 = No data overrun condition.
1. Redundant Information for the most critical bus status which is ‘CAN BusOff’. This only occurs
if the Tx Error Counter exceeds a number of 255 errors. CAN Bus Off affects the receiver state.
As soon as the transmitter leaves its Bus Off state the receiver state skips to RxOK too. Refer
also to TSTAT[1:0] coding.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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