Datasheet

MSCAN
MC9S12DP256 — Revision 1.1
MSCAN
MSCAN Receiver
Flag Register
(CANRFLG)
A flag can only be cleared when the condition which caused the setting
is no longer valid and can only be cleared by software (writing a ‘1’ to the
corresponding bit position). Every flag has an associated interrupt
enable bit in the CANRIER register.
NOTE: The CANRFLG register is held in the reset state
1
when the Initialization
Mode is active (INITRQ=1 and INITAK=1). This register is writable again
as soon as the Initialization Mode is left (INITRQ=0 and INITAK=0).
Read: anytime
Write: anytime when out of Initialization Mode, except RSTAT[1:0] &
TSTAT[1:0] flags which are read only; write of ‘1’ clears flag; write of ‘0’
ignored
WUPIF — Wake-up Interrupt Flag
If the MSCAN detects bus activity while in Sleep Mode (see MSCAN
Sleep Mode) and the WUPE=1 in CANTCTL0 (see MSCAN Control 0
Register (CANCTL0)), it will set the WUPIF flag. If not masked, a
Wake-Up interrupt is pending while this flag is set.
1 = MSCAN detected activity on the bus and requested wake-up.
0 = No wake-up activity observed while in Sleep Mode.
CSCIF — CAN Status Change Interrupt Flag
This flag is set when the MSCAN changes its current bus status due
to the actual value of the Transmit Error Counter (TEC) and the
Receive Error Counter (REC). An additional 4-bit (RSTAT[1:0],
TSTAT[1:0]) status register, which is split into separate sections for
TEC/REC, informs the system on the actual bus status (see MSCAN
Receiver Interrupt Enable Register (CANRIER)). If not masked, an
Error interrupt is pending while this flag is set. CSCIF provides a
Address Offset: $0004
Bit 7 654321Bit 0
Read:
WUPIF CSCIF
RSTAT 1 RS TAT0 TSTAT 1 TS TAT0
OVRIF RXF
Write:
Reset: 00000000
1. The RSTAT[1:0, TSTAT[1:0] bits are not affected by Initialization Mode
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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