Datasheet

MSCAN
MC9S12DP256 — Revision 1.1
MSCAN
NOTE: The MCU cannot clear the INITRQ bit before the MSCAN has entered
Initialization Mode (INITRQ=1 and INITAK=1)
CAUTION: In order to protect from accidentally violating the CAN protocol the
TxCAN pin is immediately forced to a recessive state when the
Initialization Mode is requested by the MCU. Thus the recommended
procedure is to bring the MSCAN into Sleep Mode (SLPRQ=1 and
SLPAK=1) before.
MSCAN Control 1
Register
(CANCTL1)
The CANCTL1 register provides for various control and handhake status
information of the MSCAN module as described below.
Read: anytime
Write: anytime when INITRQ=1 and
INITAK=1, except CANE which is
write once in normal modes and anytime in special modes when the
MSCAN is in Initialization Mode (INITRQ=1 and INITAK=1).
CANE — MSCAN Enable
1 = The MSCAN module is enabled.
0 = The MSCAN module is disabled.
CLKSRC — MSCAN Clock Source
This bit defines the clock source for the MSCAN module (only for
systems with a system clock generation module; see Clock System
and Figure 99).
1 = The MSCAN clock source is the ungated IPbus clock (CLK).
0 = The MSCAN clock source is the oscillator clock (OSC_CLK).
Address Offset: $0001
Bit 7 654321Bit 0
Read:
CANE CLKSRC LOOPB LISTEN
0
WUPM
SLPAK INITAK
Write:
Reset: 00010001
= Unimplemented
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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