Datasheet

MSCAN
MC9S12DP256 — Revision 1.1
MSCAN
Timer Stamp The MSCAN generates an internal time stamp whenever a valid frame
is received or transmitted and the TIME bit is enabled. Because the CAN
specification defines a frame to be valid if no errors occur before the End
of Frame (EOF) field is transmitted successfully, the actual value of an
internal timer is written at EOF to the appropriate time stamp position
within the transmit buffer. For receive frames the time stamp is written to
the receive buffer.
Register Descriptions
This section describes in detail all the registers and register bits in the
MSCAN module.
NOTE: All bits of all registers in this module are completely synchronous to
internal clocks during a register read.
ProgrammerÕs
Model of Control
Registers
The programmer’s model is laid out for maximum simplicity and
efficiency. The Register Map provides an overview of the control
registers for the MSCAN.
MSCAN Control 0
Register
(CANCTL0)
The CANCTL0 register provides for various control of the MSCAN
module as described below.
NOTE: The CANCTL0 register, except the WUPE, INITRQ and SLPRQ bits, is
held in the reset state when the Initialization Mode is active (INITRQ=1
and INITAK=1). This register is writable again as soon as the
Initialization Mode is left (INITRQ=0 and INITAK=0).
Address Offset: $0000
Bit 7 654321Bit 0
Read:
RXFRM
RXACT
CSWAI
SYNCH
TIME WUPE SLPRQ INITRQ
Write:
Reset: 00000001
= Unimplemented
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Freescale Semiconductor, Inc.
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