Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

MSCAN
Functional Description
MC9S12DP256 — Revision 1.1
MSCAN
The Synchronization Jump Width
1
can be programmed in a range of 1
to 4 time quanta by setting the SJW parameter.
The above parameters are set by programming the MSCAN Bus Timing
Registers (CANBTR0, CANBTR1) (see MSCAN Bus Timing Register 0
(CANBTR0) and MSCAN Bus Timing Register 1 (CANBTR1)).
Figure 101 gives an overview of the CAN compliant segment settings
and the related parameter values.
NOTE:
It is the user’s responsibility to ensure the bit time settings are in
compliance with the CAN standard.
Table 86 Time Segment Syntax
Syntax Description
SYNC_SEG
System expects transitions to occur on the bus during this
period.
Transmit Point
A node in transmit mode transfers a new value to the CAN
bus at this point.
Sample Point
A node in receive mode samples the bus at this point. If the
three samples per bit option is selected, then this point
marks the position of the third sample.
1. Reference the Bosch CAN 2.0A/B protocol specification dated September 1991 for bit timing.
Time
Segment 1
TSEG1
Time
Segment 2
TSEG2
Synchronization
Jump Width
SJW
5 .. 10 4 .. 9 2 1 1 .. 2 0 .. 1
4 .. 11 3 .. 10 3 2 1 .. 3 0 .. 2
5 .. 12 4 .. 11 4 3 1 .. 4 0 .. 3
6 .. 13 5 .. 12 5 4 1 .. 4 0 .. 3
7 .. 14 6 .. 13 6 5 1 .. 4 0 .. 3
8 .. 15 7 .. 14 7 6 1 .. 4 0 .. 3
9 .. 16 8 .. 15 8 7 1 .. 4 0 .. 3
Figure 101 CAN Standard Compliant Bit Time Segment Settings
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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