Datasheet

MSCAN
Functional Description
MC9S12DP256 — Revision 1.1
MSCAN
Figure 99 MSCAN Clocking Scheme
The Clock Source bit (CLKSRC) in the CANCTL1 register (see MSCAN
Control 1 Register (CANCTL1)) defines whether the internal CAN_CLK
is connected to the output of a crystal oscillator (OSC_CLK) or to the
IPbus bus clock (CLK).
The clock source has to be chosen such that the tight oscillator tolerance
requirements (up to 0.4%) of the CAN protocol are met. Additionally, for
high CAN bus rates (1 Mbps), a 45%-55% duty cycle of the clock is
required.
NOTE: If the system clock is generated from a PLL, it is recommended to select
the crystal clock source rather than the system clock source due to jitter
considerations, especially at the faster CAN bus rates.
For microcontrollers without a clock and reset generator (CRG),
CAN_CLK is driven from the crystal oscillator (OSC_CLK).
A programmable prescaler generates the time quanta (Tq) clock from
CAN_CLK. A time quantum is the atomic unit of time handled by the
MSCAN.
A bit time is subdivided into three segments
1 2
(see Figure 100):
IPbus CLK
OSC_CLK
MSCAN
IPbus
Bus Interface
(IPBI)
CAN_CLK
CLKSRC
CLKSRC
Prescaler
(1... 64)
Time quanta clock (Tq)
f
Tq
f
CANCLK
Prescaler value◊()
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Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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