Datasheet

MSCAN
MC9S12DP256 — Revision 1.1
MSCAN
Protocol Violation
Protection
The MSCAN protects the user from accidentally violating the CAN
protocol through programming errors. The protection logic implements
the following features:
• The receive and transmit error counters cannot be written or
otherwise manipulated.
• All registers which control the configuration of the MSCAN cannot
be modified while the MSCAN is on-line. The MSCAN has to be in
Initialization Mode. The corresponding INITRQ/INITAK
handshake bits in the CANCTL0/CANCTL1 registers (see
MSCAN Control 0 Register (CANCTL0)) serve as a lock to protect
the following registers:
– MSCAN Control 1 Register (CANCTL1)
– MSCAN Bus Timing Registers 0 and 1 (CANBTR0, CANBTR1)
– MSCAN Identifier Acceptance Control Register (CANIDAC)
– MSCAN Identifier Acceptance Registers (CANIDAR0–7)
– MSCAN Identifier Mask Registers (CANIDMR0–7)
• The TxCAN pin is immediately forced to a recessive state when
the MSCAN goes into the Power Down Mode or Initialization Mode
(see MSCAN Power Down Mode and MSCAN Initialization Mode).
• The MSCAN enable bit (CANE) is only writable once in normal
modes as further protection against inadvertently disabling the
MSCAN.
Clock System Figure 99 shows the structure of the MSCAN clock generation circuitry.
With this flexible clocking scheme, the MSCAN is able to handle CAN
bus rates ranging from 10 Kbps up to 1 Mbps.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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