Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

MSCAN
MC9S12DP256 — Revision 1.1
MSCAN
Identifier
Acceptance Filter
The MSCAN Identifier Acceptance Registers (see MSCAN Identifier
Acceptance Registers (CANIDAR0–7)) define the acceptable patterns of
the standard or extended identifier (ID10–ID0 or ID28–ID0). Any of these
bits can be marked ‘don’t care’ in the MSCAN Identifier Mask Registers
(see MSCAN Identifier Mask Registers (CANIDMR0–7)).
A filter hit is indicated to the application software by a set Receive Buffer
Full flag (RXF=1) and three bits in the CANIDAC register (see MSCAN
Identifier Acceptance Control Register (CANIDAC)). These Identifier Hit
flags (IDHIT2–0) clearly identify the filter section that caused the
acceptance. They simplify the application software’s task to identify the
cause of the receiver interrupt. In case more than one hit occurs (two or
more filters match), the lower hit has priority.
A very flexible programmable generic identifier acceptance filter has
been introduced to reduce the CPU interrupt loading. The filter is
programmable to operate in four different modes
1
:
• Two identifier acceptance filters, each to be applied to a) the full
29 bits of the extended identifier and to the following bits of the
CAN 2.0B frame: Remote Transmission Request (RTR), Identifier
Extension (IDE), and Substitute Remote Request (SRR) or b)
2
the
11 bits of the standard identifier plus the RTR and IDE bits of the
CAN 2.0A/B messages. This mode implements two filters for a full
length CAN 2.0B compliant extended identifier. Figure 96 shows
how the first 32-bit filter bank (CANIDAR0–3, CANIDMR0–3)
produces a filter 0 hit. Similarly, the second filter bank
(CANIDAR4–7, CANIDMR4–7) produces a filter 1 hit.
• Four identifier acceptance filters, each to be applied to a) the 14
most significant bits of the extended identifier plus the SRR and
IDE bits of CAN 2.0B messages or b) the 11 bits of the standard
identifier, the RTR and IDE bits of CAN 2.0A/B messages.
Figure 97 shows how the first 32-bit filter bank (CANIDAR0–3,
1. For a better understanding of references made within the filter mode description, reference the
Bosch specification dated September 1991 which details the CAN 2.0A/B protocol.
2. Although this mode can be used for standard identifiers, it is recommended to use the four or
eight identifier acceptance filters for standard identifiers
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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