Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

MSCAN
Functional Description
MC9S12DP256 — Revision 1.1
MSCAN
RxBG. After successful reception of a valid message the MSCAN shifts
the content of RxBG into the receiver FIFO
1
, sets the RXF flag, and
generates a receive interrupt (see Interrupt Operation) to the CPU
2
. The
user’s receive handler has to read the received message from the RxFG
and then reset the RXF flag to acknowledge the interrupt and to release
the foreground buffer. A new message, which can follow immediately
after the IFS field of the CAN frame, is received into the next available
RxBG. If the MSCAN receives an invalid message in its RxBG (wrong
identifier, transmission errors etc.) the actual contents of the buffer will
be over-written by the next message. The buffer will then not be shifted
into the FIFO.
When the MSCAN module is transmitting, the MSCAN receives its own
transmitted messages into the background receive buffer, RxBG, but
does not shift it into the receiver FIFO, generate a receive interrupt, or
acknowledge its own messages on the CAN bus. The exception to this
rule is in loop back mode (see MSCAN Control 1 Register (CANCTL1))
where the MSCAN treats its own messages exactly like all other
incoming messages. The MSCAN receives its own transmitted
messages in the event that it loses arbitration
3
. If arbitration is lost, the
MSCAN must be prepared to become a receiver.
An overrun condition occurs when all receive message buffers in the
FIFO are filled with correctly received messages with accepted
identifiers and another message is correctly received from the bus with
an accepted identifier. The latter message is discarded and an error
interrupt with overrun indication is generated if enabled (see Interrupt
Operation). The MSCAN is still able to transmit messages while the
receiver FIFO being filled, but all incoming messages are discarded. As
soon as a receive buffer in the FIFO is available again, new valid
messages will be accepted.
1. As long as the FIFO Buffer is not completely filled.
2. The receive interrupt occurs only if not masked. A polling scheme can be applied on RXF also.
3. Reference the Bosch CAN 2.0A/B protocol specification dated September 1991 for details.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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