Datasheet

Pinout and Signal Description
MC9S12DP256 — Revision 1.1
Pinout and Signal Description
vector ($FFFE:FFFF) is taken when RESET is finally released. If RESET
is high after this 32 cycle delay, the reset source is tentatively assumed
to be either a COP failure or a clock monitor failure. If the internally
latched state of the clock monitor fail circuit is true, processing begins by
fetching the clock monitor vector ($FFFC:FFFD). If no clock monitor
failure is indicated, and the latched state of the COP timeout is true,
processing begins by fetching the COP vector ($FFFA:FFFB). If neither
clock monitor fail nor COP timeout are pending, processing begins by
fetching the normal reset vector ($FFFE:FFFF).
Maskable
Interrupt Request
(IRQ
)
The IRQ
input provides a means of applying asynchronous interrupt
requests to the MCU. Either falling edge-sensitive triggering or
level-sensitive triggering is program selectable (INTCR register). IRQ
is
always enabled and configured to level-sensitive triggering out of reset.
It can be disabled by clearing IRQEN bit (INTCR register). When the
MCU is reset the IRQ
function is masked in the condition code register.
This pin is always an input and can always be read. There is an active
pull-up on this pin while in reset and immediately out of reset. The pullup
can be turned off by clearing PUPEE in the PUCR register.
Nonmaskable
Interrupt (XIRQ
)
The XIRQ
input provides a means of requesting a nonmaskable interrupt
after reset initialization. During reset, the X bit in the condition code
register (CCR) is set and any interrupt is masked until MCU software
enables it. Because the XIRQ
input is level sensitive, it can be connected
to a multiple-source wired-OR network. This pin is always an input and
can always be read. There is an active pull-up on this pin while in reset
and immediately out of reset. The pullup can be turned off by clearing
PUPEE in the PUCR register. XIRQ
is often used as a power loss detect
interrupt.
Whenever XIRQ or IRQ are used with multiple interrupt sources, (IRQ
must be configured for level-sensitive operation if there is more than one
source of IRQ
interrupt), each source must drive the interrupt input with
an open-drain type of driver to avoid contention between outputs. There
must also be an interlock mechanism at each interrupt source so that the
source holds the interrupt line low until the MCU recognizes and
acknowledges the interrupt request. If the interrupt line is held low, the
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