Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller QFP 80 (14x14) 16-Bit 25 MHz I/O number 59

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Table Of Contents

List of Sections
Table of Contents
General Description
- Contents
- Introduction
- Features
- MC9S12DP256 112-Pin Block Diagram
- Ordering Information
Central Processing Unit (CPU)
- Contents
- Introduction
- Programming Model
- Data Types
- Addressing Modes
- Indexed Addressing Modes
- Opcodes and Operands
- Instruction Set Summary
Pinout and Signal Description
- Contents
- MC9S12DP256 Pin Assignments in 112-pin QFP
- Power Supply Pins
- Signal Descriptions
- Port Signals
System Configuration
- Contents
- Introduction
- Modules Variabilities
- MCU Variabilities
Registers
- Contents
- Register Block
Operating Modes
- Contents
- Introduction
- Operating Modes
- Background Debug Mode
- Security
Resource Mapping
- Contents
- Introduction
- Internal Resource Mapping
- Flash EEPROM mapping through internal Memory Expansion
- Miscellaneous System Control Register
- Memory Maps
Bus Control and Input/Output
- Contents
- Introduction
- Detecting Access Type from External Signals
- Stretched Bus Cycles
- PIPE Status Signals
- Registers
Resets and Interrupts
- Contents
- Introduction
- Register Map
- Exception Priority
- Maskable interrupts
- Latching of Interrupts
- Register Descriptions
- Resets
- Effects of Reset
- Register Stacking
Voltage Regulator (VREG)
- Contents
- Overview
- Features
- Block Diagram
- Functional Description
- External Pin Connection
- Reset Initialization
- Modes of Operation
Flash EEPROM 256K
- Contents
- Glossary
- Overview
- Features
- Block Diagram
- Module Memory Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization
- Modes of Operation
- Low Power Options
- Interrupt Operation
EEPROM 4K
- Contents
- Glossary
- Overview
- Features
- Block Diagram
- Module Memory Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization
- Modes of Operation
- Interrupt Operation
Port Integration Module
- Contents
- Overview
- Block Diagram
- External Pin Descriptions
- 80 Pin QFP bond-out version
- Register Map
- Register Descriptions
- Reset Initialization
- Functional Description
- Low Power Options
- Interrupt Operation
Clocks and Reset Generator (CRG)
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization
- Interrupt Operation
- Low Power Options
Pulse Width Modulator (PWM)
- Contents
- Overview
- Features
- Block Diagram
- External Pin Descriptions
- Register Map
- Register Descriptions
- Functional Description
- Reset Initialization
- Modes of Operation
- Low Power Options
- Interrupt Operation
Enhanced Capture Timer (ECT)
- Contents
- Overview
- Features
- Modes of Operation
- Abbreviations
- Block Diagram
- Signal Descriptions
- Module Memory Map
- Register Quick Reference
- Register Descriptions
- Modes of Operation
- Interrupts
- Description of Interrupt Operation
Serial Communications Interface (SCI)
- Contents
- Overview
- Features
- Modes of Operation
- SCI Interface Diagram
- Block Diagram
- Signal Descriptions
- Module Memory Map
- Register Quick Reference
- Register Descriptions
- Functional Description
- Modes of Operation
- Interrupt Operation
Serial Peripheral Interface (SPI)
- Contents
- Overview
- Features
- Modes of Operation
- Block Diagram
- Signal Descriptions
- Module Memory Map
- Register Quick Reference
- Register Descriptions
- Functional Description
- Low Power Mode Options
- Errata
- Reset
- Interrupts
Inter-IC Bus (IIC)
- Contents
- Overview
- Features
- Modes of Operation
- Block Diagram
- Signal Descriptions
- Module Memory Map
- Register Quick Reference
- Register Descriptions
- I-Bus Protocol
- Interrupt Operation
- Modes of Operation
- Programming
MSCAN
- Contents
- Overview
- Features
- Block Diagram
- External Pin Descriptions
- Register Map
- Functional Description
- Register Descriptions
- Modes of Operation
- Low Power Options
- Interrupt Operation
Analog to Digital Converter
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization
- Modes of Operation
- Sample Conversion
- General Purpose Input Ports
Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
Background Debug Module (BDM)
- Contents
- Overview
- Interface Signals
- Registers
- Operation
- Modes of Operation
- Low-Power Options
- Interrupt Operation
Breakpoint (BKP) Module
- Contents
- Overview
- Features
- Block Diagram
- External Pin Descriptions
- Register Descriptions
- Functional Description
- Breakpoint Operating Modes
- Breakpoint Types
- Modes of Operation
- Low Power Options
- Reset Initialization
- Interrupt Operation
- General Purpose I/O Ports
Revision History
- Changes from Rev 1.0 to Rev 1.1
Glossary
Literature Updates
- Literature Distribution Centers
- Customer Focus Center
- Microcontroller Division’s Web Site

MSCAN

MC9S12DP256 — Revision 1.1

MSCAN

Reserved bits within a register always read as 0 and a write is

unimplemented

. Unimplemented functions are indicated by shading the

bit.

1. Reserved bits within the Tx- & Rx-Buffers (CANTXFG, CANRXFG) will be read as ‘X’, because

of RAM based implementation.

Addr.

Offset

CANCTL0

Read:

RXFRM

RXACT

CSWAI

SYNCH

TIME WUPE SLPRQ INITRQ $0000

Write:

CANCTL1

Read:

CANE CLKSRC LOOPB LISTEN

WUPM

SLPAK INITAK

$0001

Write:

CANBTR0

Read:

SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 $0002

Write:

CANBTR1

Read:

SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 $0003

Write:

CANRFLG

Read:

WUPIF CSCIF

RSTAT 1 RS TAT0 TSTAT 1 TS TAT0

OVRIF RXF $0004

Write:

CANRIER

Read:

WUPIE CSCIE RSTATE1 RSTATE0 TSTATE1 TSTATE0 OVRIE RXFIE $0005

Write:

CANTFLG

TXE2 TXE1 TXE0 $0006

Write:

CANTIER

TXEIE2 TXEIE1 TXEIE0 $0007

Write:

CANTARQ

ABTRQ2 ABTRQ1 ABTRQ0 $0008

Write:

CANTAAK

Read: 00000ABTAK2ABTAK1ABTAK0

$0009

Write:

CANTBSEL

TX2 TX1 TX0 $000A

Write:

CANIDAC

IDAM1 IDAM0

0 IDHIT2 IDHIT1 IDHIT0

$000B

Write:

RESERVED

$000C

-$000D

Write:

CANRXERR

Read: RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0

$000E

Write:

CANTXERR

Read: TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0

$000F

Write:

CANIDAR0

Read:

AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 $0010

Write:

= Unimplemented

Figure 94 MSCAN Register Map

Freescale Semiconductor, I

Freescale Semiconductor, Inc.

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Go to: www.freescale.com

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