Datasheet

Pinout and Signal Description
Signal Descriptions
MC9S12DP256 — Revision 1.1
Pinout and Signal Description
Reset (RESET) RESET is an active low bidirectional control signal that acts as an input
to initialize the MCU to a known start-up state. It also acts as an
open-drain output to indicate that an internal failure has been detected
in either the clock monitor or COP watchdog circuit. The MCU goes into
reset asynchronously and comes out of reset synchronously. This allows
the part to reach a proper reset state even if the clocks have failed, while
allowing synchronized operation when starting out of reset.
It is important to use an external low-voltage reset circuit (similar to
MC33464-48) to prevent corruption of RAM or EEPROM due to power
transitions.
The reset sequence is initiated by any of the following events:
• Clock monitor enabled and clock monitor detects slow or stopped
clock
• COP watchdog enabled and watchdog timer times out
• Power-on Reset (POR)
• User applies a low level to the RESET
pin
External circuitry connected to the RESET
pin should not include a large
capacitance that would interfere with the ability of this signal to rise to a
valid logic one within 32 ECLK cycles after the low drive is released.
Upon detection of any reset, an internal circuit drives the RESET
pin low
and a clocked reset sequence controls when the MCU can begin normal
processing.
NOTE: Entry into reset is asynchronous and does not require a clock. However,
the MCU cannot sequence out of reset without a system clock.
In the case of POR or a clock monitor failure a 4096 ECLK cycle
oscillator startup delay is imposed before the reset recovery sequence
starts (RESET
is driven low throughout this 4096 cycle delay.) The
internal reset recovery sequence then drives RESET
low for 64 to 65
ECLK cycles and releases the drive to allow RESET
to rise. 32 ECLK
cycles later this circuit samples the RESET
pin to see if it has risen to a
logic one level. If RESET
is low at this point, the reset is assumed to be
coming from an external request and the internally latched states of the
COP timeout and clock monitor failure are cleared so the normal reset
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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