Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates
Inter-IC Bus (IIC)
MC9S12DP256 — Revision 1.1
Inter-IC Bus (IIC)
An example of a program which generates the START signal and
transmits the first byte of data (slave address) is shown below:
Post-Transfer
Software
Response
Transmission or reception of a byte by the IIC will set the data
transferring bit (TCF) to 1, which indicates one byte communication is
finished. The IIC interrupt bit (IBIF) is set also; an interrupt will be
generated if the interrupt function is enabled during initialization by
setting the IBIE bit. Software must clear the IBIF bit in the interrupt
routine first. The TCF bit will be cleared by reading from the IIC Data I/O
Register (IBDR) in receive mode or writing to IBDR in transmit mode.
Software may service the IIC I/O in the main program by monitoring the
IBIF bit if the interrupt function is disabled. Note that polling should
monitor the IBIF bit rather than the TCF bit since their operation is
different when arbitration is lost.
Note that when an interrupt occurs at the end of the address cycle the
master will always be in transmit mode, i.e. the address is transmitted. If
master receive mode is required, indicated by R/W
bit in IBDR, then the
Tx/Rx
bit should be toggled at this stage.
During slave mode address cycles (IAAS=1) the SRW bit in the status
register is read to determine the direction of the subsequent transfer and
the Tx/Rx
bit is programmed accordingly. For slave mode data cycles
(IAAS=0) the SRW bit is not valid, the Tx/Rx
bit in the control register
should be read to determine the direction of the current transfer.
The following is an example of a software response by a ‘master
transmitter’ in the interrupt routine (see Figure 90).
CHFLAG BRSET IBSR,#$20, * ;WAIT FOR IBB FLAG TO CLEAR
TXSTART BSET IBCR,#$30 ;SET TRANSMIT AND MASTER MODE
;i.e. GENERATE START CONDITION
MOVEB CALLING,IBDR ;TRANSMIT THE CALLING
;ADDRESS, D0=R/W
IBFREE BRCLR #5,IBSR,#$20,* ;WAIT FOR IBB FLAG TO SET
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