Datasheet

Inter-IC Bus (IIC)
Programming
MC9S12DP256 — Revision 1.1
Inter-IC Bus (IIC)
Programming
Initialization
Sequence
Reset will put the IIC Control Register to its default status. Before the
interface can be used to transfer serial data, an initialization procedure
must be carried out, as follows:
1. Update the Frequency Divider Register (IBFD) and select the
required division ratio to obtain SCL frequency from system clock.
2. Update the IIC Address Register (IBAD) to define its slave
address.
3. Set the IBEN bit of the IIC Control Register (IBCR) to enable the
IIC system.
4. Modify the bits of the IIC Control Register (IBCR) to select
Master/Slave mode, Transmit/Receive mode and interrupt enable
or not.
Generation of
START
After completion of the initialization procedure, serial data can be
transmitted by selecting the ‘master transmitter’ mode. If the device is
connected to a multi-master bus system, the state of the IIC Busy Bit
(IBB) must be tested to check whether the serial bus is free.
If the bus is free (IBB=0), the start condition and the first byte (the slave
address) can be sent. The data written to the data register comprises the
slave calling address and the LSB set to indicate the direction of transfer
required from the slave.
The bus free time (i.e., the time between a STOP condition and the
following START condition) is built into the hardware that generates the
START cycle. Depending on the relative frequencies of the system clock
and the SCL period it may be necessary to wait until the IIC is busy after
writing the calling address to the IBDR before proceeding with the
following instructions. This is illustrated in the following example.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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