Datasheet

Inter-IC Bus (IIC)
MC9S12DP256 — Revision 1.1
Inter-IC Bus (IIC)
This bit must be cleared by software, by writing a low to it.
Byte Transfer
Interrupt
After completion of byte transfer, TCF (Data Transfer) bit is set at the
falling edge of the 9th clock to indicate the completion of Byte Transfer.
Address Detect
Interrupt
When its own specific address (I-Bus Address Register) is matched with
the calling address, IAAS bit in Status register is set. The CPU is
interrupted provided the IBIE is set. Then the CPU needs to check the
SRW bit and set its Tx/Rx mode accordingly.
Modes of Operation
The IIC functions the same in normal, special, and emulation modes. It
has two low power modes, wait and stop modes.
Run Mode This is the basic mode of operation.
Wait Mode IIC operation in wait mode is a configurable low power mode. Depending
on the state of internal bits, the IIC can operate normally when the CPU
is in wait mode or the IIC clock generation can be turned off and the IIC
module enters a power conservation state during wait mode. In the later
case, any transmission or reception in progress stops at wait mode
entry.
Stop Mode The IIC is inactive in stop mode for reduced power consumption. The
STOP instruction does not affect IIC register states.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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