Datasheet

Inter-IC Bus (IIC)
Interrupt Operation
MC9S12DP256 — Revision 1.1
Inter-IC Bus (IIC)
Interrupt Operation
System Level
Interrupt Sources
There is one interrupt signal that is sent from the IIC to the core.
Interrupt
Descriptions
See the Interrupts section of the End User Guide, which describes the
Interrupt signals generated by the IIC Status registers.
Internally there are three types of interrupts. These are generated on
1. Arbitration Lost Interrupt
2. Byte Transfer Interrupt
3. Address Detect Interrupt
There is only one interrupt signal iic_int to core. The interrupt is driven
by Bit IBIF (of the IIC Status Register) and masked with bit IBIE (of the
IIC Control Register). This bit must be cleared by software by writing a
low to it in the interrupt routine. core can determine the Interrupt type
after reading the Status Register.
Arbitration Lost
Interrupt
The Inter-IC bus is a true multi-master bus that allows more than one
master to be connected on it. If two or more masters try to control the
bus at the same time, the relative priority of the contending masters is
determined by a data arbitration procedure. The IIC module asserts this
interrupt when It loses the data arbitration process. And IBAL bit in
Status Register is also set.
Arbitration is lost in the following circumstances:
1. SDA sampled as a low when the master drives a high during an
address or data transmit cycle.
2. SDA sampled as a low when the master drives a high during the
acknowledge bit of a data receive cycle.
3. A start cycle is attempted when the bus is busy.
4. A repeated start cycle is requested in slave mode.
5. A stop condition is detected when the master did not request it.
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