Datasheet

Inter-IC Bus (IIC)
MC9S12DP256 — Revision 1.1
Inter-IC Bus (IIC)
state during this time (see Figure 89). When all devices concerned have
counted off their low period, the synchronized clock SCL line is released
and pulled high. There is then no difference between the device clocks
and the state of the SCL line and all the devices start counting their high
periods. The first device to complete its high period pulls the SCL line low
again.
Figure 89 I-Bus Clock Synchronization
Handshaking The clock synchronization mechanism can be used as a handshake in
data transfer. Slave devices may hold the SCL low after completion of
one byte transfer (9 bits). In such case, it halts the bus clock and forces
the master clock into wait states until the slave releases the SCL line.
Clock Stretching The clock synchronization mechanism can be used by slaves to slow
down the bit rate of a transfer. After the master has driven SCL low the
slave can drive SCL low for the required period and then release it. If the
slave SCL low period is greater than the master SCL low period then the
resulting SCL bus signal low period is stretched.
SCL1
SCL2
SCL
Internal Counter Reset
WAIT
Start Counting High Period
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