Datasheet

Inter-IC Bus (IIC)
I-Bus Protocol
MC9S12DP256 — Revision 1.1
Inter-IC Bus (IIC)
STOP Signal The master can terminate the communication by generating a STOP
signal to free the bus. However, the master may generate a START
signal followed by a calling command without generating a STOP signal
first. This is called repeated START. A STOP signal is defined as a
low-to-high transition of SDA while SCL at logical “1” (see Figure 88).
The master can generate a STOP even if the slave has generated an
acknowledge at which point the slave must release the bus.
Repeated START
Signal
As shown in Figure 88, a repeated START signal is a START signal
generated without first generating a STOP signal to terminate the
communication. This is used by the master to communicate with another
slave or with the same slave in different mode (transmit/receive mode)
without releasing the bus.
Arbitration
Procedure
The Inter-IC bus is a true multi-master bus that allows more than one
master to be connected on it. If two or more masters try to control the
bus at the same time, a clock synchronization procedure determines the
bus clock, for which the low period is equal to the longest clock low
period and the high is equal to the shortest one among the masters. The
relative priority of the contending masters is determined by a data
arbitration procedure, a bus master loses arbitration if it transmits logic
“1” while another master transmits logic “0”. The losing masters
immediately switch over to slave receive mode and stop driving SDA
output. In this case the transition from master to slave mode does not
generate a STOP condition. Meanwhile, a status bit is set by hardware
to indicate loss of arbitration.
Clock
Synchronization
Since wire-AND logic is performed on SCL line, a high-to-low transition
on SCL line affects all the devices connected on the bus. The devices
start counting their low period and once a device's clock has gone low,
it holds the SCL line low until the clock high state is reached. However,
the change of low to high in this device clock may not change the state
of the SCL line if another device clock is still within its low period.
Therefore, synchronized clock SCL is held low by the device with the
longest low period. Devices with shorter low periods enter a high wait
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Freescale Semiconductor, Inc.
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