Datasheet

Inter-IC Bus (IIC)
MC9S12DP256 — Revision 1.1
Inter-IC Bus (IIC)
1 = Read transfer, the slave transmits data to the master.
0 = Write transfer, the master transmits data to the slave.
Only the slave with a calling address that matches the one transmitted
by the master will respond by sending back an acknowledge bit. This is
done by pulling the SDA low at the 9th clock (see Figure 88).
No two slaves in the system may have the same address. If the IIC Bus
is master, it must not transmit an address that is equal to its own slave
address. The IIC Bus cannot be master and slave at the same time.
However, if arbitration is lost during an address cycle the IIC Bus will
revert to slave mode and operate correctly even if it is being addressed
by another master.
Data Transfer Once successful slave addressing is achieved, the data transfer can
proceed byte-by-byte in a direction specified by the R/W bit sent by the
calling master.
All transfers that come after an address cycle are referred to as data
transfers, even if they carry sub-address information for the slave
device.
Each data byte is 8 bits long. Data may be changed only while SCL is
low and must be held stable while SCL is high as shown in Figure 88.
There is one clock pulse on SCL for each data bit, the MSB being
transferred first. Each data byte has to be followed by an acknowledge
bit, which is signalled from the receiving device by pulling the SDA low
at the ninth clock. So one complete data byte transfer needs nine clock
pulses.
If the slave receiver does not acknowledge the master, the SDA line
must be left high by the slave. The master can then generate a stop
signal to abort the data transfer or a start signal (repeated start) to
commence a new calling.
If the master receiver does not acknowledge the slave transmitter after
a byte transmission, it means ‘end of data’ to the slave, so the slave
releases the SDA line for the master to generate STOP or START signal.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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