Datasheet

Pinout and Signal Description
MC9S12DP256 — Revision 1.1
Pinout and Signal Description
port PE7 (XCLKS) low during the reset phase the internal low current
oscillator is bypassed and an internal buffer driven by EXTAL feeds the
internal clocks. The XTAL output is normally intended to drive only a
crystal. The XTAL output can be buffered with a high-impedance buffer
to drive the EXTAL input of another device. The maximum output voltage
of this pin is VDDPLL.
In all cases take extra care in the circuit board layout around the
oscillator pins. Load capacitances in the oscillator circuits include all
stray layout capacitances. Refer to Figure 6 and Figure 7 for diagrams
of oscillator circuits.
E-Clock Output
(ECLK)
ECLK is the output connection for the internal bus clock. It is used to
demultiplex the address and data in expanded modes and is used as a
timing reference. ECLK frequency is equal to 1/2 the crystal frequency
out of reset. The ECLK pin is initially configured as ECLK output with
stretch in all expanded modes. The E clock output function depends
upon the settings of the NECLK bit in the PEAR register, the IVIS bit in
the MODE register and the ESTR bit in the EBICTL register. All clocks,
including the E clock, are halted when the MCU is in STOP mode. It is
possible to configure the MCU to interface to slow external memory.
ECLK can be stretched for such accesses. Reference the MISC register
(EXSTR[1:0] bits) for more information. In normal expanded narrow
mode, the E clock is available for use in external select decode logic or
as a constant speed clock for use in the external application system.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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