Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Inter-IC Bus (IIC)
I-Bus Protocol
MC9S12DP256 — Revision 1.1
Inter-IC Bus (IIC)
Normally, a standard communication is composed of four parts: START
signal, slave address transmission, data transfer and STOP signal. They
are described briefly in the following sections and illustrated in Figure 88.
Figure 88 I-Bus Transmission Signals
START Signal When the bus is free, i.e. no master device is engaging the bus (both
SCL and SDA lines are at logical high), a master may initiate
communication by sending a START signal. As shown in Figure 88, a
START signal is defined as a high-to-low transition of SDA while SCL is
high. This signal denotes the beginning of a new data transfer (each data
transfer may contain several bytes of data) and brings all slaves out of
their idle states.
Slave Address
Transmission
The first byte of data transfer immediately after the START signal is the
slave address transmitted by the master. This is a seven-bit calling
address followed by a R/W bit. The R/W bit tells the slave the desired
direction of data transfer.
SCL
SDA
Start
Signal
Ack
Bit
12345678
MSB LSB
12345678
MSB LSB
Stop
Signal
No
SCL
SDA
12345678
MSB LSB
12 5 678
MSB LSB
Repeated
34
9 9
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XXX D7 D6 D5 D4 D3 D2 D1 D0
Calling Address Read/ Data Byte
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
New Calling Address
99
XX
Ack
Bit
Write
Start
Signal
Start
Signal
Ack
Bit
Calling Address Read/
Write
Stop
Signal
No
Ack
Bit
Read/
Write
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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