Datasheet

Inter-IC Bus (IIC)
MC9S12DP256 — Revision 1.1
Inter-IC Bus (IIC)
IIC Data I/O
Register (IBDR)
In master transmit mode, when data is written to the IBDR a data transfer
is initiated. The most significant bit is sent first. In master receive mode,
reading this register initiates next byte data receiving. In slave mode, the
same functions are available after an address match has occurred. Note
that the Tx/Rx bit in the IBCR must correctly reflect the desired direction
of transfer in master and slave modes for the transmission to begin. For
instance, if the IIC is configured for master transmit but a master receive
is desired, then reading the IBDR will not initiate the receive.
Reading the IBDR will return the last byte received while the IIC is
configured in either master receive or slave receive modes. The IBDR
does not reflect every byte that is transmitted on the IIC bus, nor can
software verify that a byte has been written to the IBDR correctly by
reading it back.
In master transmit mode, the first byte of data written to IBDR following
assertion of MS/SL
is used for the address transfer and should comprise
of the calling address (in position D7-D1) concatenated with the required
R/W
bit (in position D0).
I-Bus Protocol
The IIC Bus system uses a Serial Data line (SDA) and a Serial Clock
Line (SCL) for data transfer. All devices connected to it must have open
drain or open collector outputs. Logic AND function is exercised on both
lines with external pull-up resistors, the value of these resistors is system
dependent.
Address Offset: $0004
Bit 7 654321Bit 0
D7 D6 D5 D4 D3 D2 D1 D0
Reset:
00000000
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...