Datasheet

Inter-IC Bus (IIC)
MC9S12DP256 — Revision 1.1
Inter-IC Bus (IIC)
IAAS — Addressed as a slave bit
When its own specific address (I-Bus Address Register) is matched
with the calling address, this bit is set. The CPU is interrupted
provided the IBIE is set. Then the CPU needs to check the SRW bit
and set its Tx/Rx
mode accordingly. Writing to the I-Bus Control
Register clears this bit.
1 = Addressed as a slave
0 = Not addressed
IBB — Bus busy bit
This bit indicates the status of the bus. When a START signal is
detected, the IBB is set. If a STOP signal is detected, it is cleared.
1 = Bus is busy
0 = Bus is idle
IBAL — Arbitration Lost
The arbitration lost bit (IBAL) is set by hardware when the arbitration
procedure is lost. Arbitration is lost in the following circumstances:
1. SDA sampled as a low when the master drives a high during an
address or data transmit cycle.
2. SDA sampled as a low when the master drives a high during the
acknowledge bit of a data receive cycle.
3. A start cycle is attempted when the bus is busy.
4. A repeated start cycle is requested in slave mode.
5. A stop condition is detected when the master did not request it.
This bit must be cleared by software, by writing a low to it.
RESERVED
Bit 3 of IBSR is reserved for future use. A read operation on this bit
will return 0.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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