Datasheet

Inter-IC Bus (IIC)
Register Descriptions
MC9S12DP256 — Revision 1.1
Inter-IC Bus (IIC)
0 = IIC Bus module clock operates normally
Wait mode is entered via execution of a CPU WAI instruction. In the
event that the IBSWAI bit is set, all clocks internal to the IIC will be
stopped and any transmission currently in progress will halt. If the
CPU were woken up by a source other than the IIC module, then
clocks would restart and the IIC would continue where it left off in the
previous transmission. It is not possible for the IIC to wake up the
CPU when its internal clocks are stopped.
If it were the case that the IBSWAI bit was cleared when the WAI
instruction was executed, the IIC internal clocks and interface would
remain alive, continuing the operation which was currently underway.
It is also possible to configure the IIC such that it will wake up the CPU
via an interrupt at the conclusion of the current operation. See the
discussion on the IBIF and IBIE bits in the IBSR and IBCR,
respectively.
IIC Status Register
(IBSR)
This status register is read-only with exception of bit 1 (IBIF) and bit 4
(IBAL), which are software clearable
TCF — Data transferring bit
While one byte of data is being transferred, this bit is cleared. It is set
by the falling edge of the 9th clock of a byte transfer. Note that this bit
is only valid during or immediately following a transfer to the IIC
module or from the IIC module.
1 = Transfer complete
0 = Transfer in progress
Address Offset: $0003
Bit 7 654321Bit 0
TCF IAAS IBB IBAL 0 SRW IBIF RXAK
Reset:
10000000
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