Datasheet

Inter-IC Bus (IIC)
MC9S12DP256 — Revision 1.1
Inter-IC Bus (IIC)
generated and the operation mode changes from master to slave.
MS/SL
is cleared without generating a STOP signal when the master
loses arbitration.
1 = Master Mode
0 = Slave Mode
Tx/Rx
— Transmit/Receive mode select bit
This bit selects the direction of master and slave transfers. When
addressed as a slave this bit should be set by software according to
the SRW bit in the status register. In master mode this bit should be
set according to the type of transfer required. Therefore, for address
cycles, this bit will always be high.
1 = Transmit
0 = Receive
TXAK — Transmit Acknowledge enable
This bit specifies the value driven onto SDA during data acknowledge
cycles for both master and slave receivers. The IIC module will always
acknowledge address matches, provided it is enabled, regardless of
the value of TXAK. Note that values written to this bit are only used
when the IIC Bus is a receiver, not a transmitter.
1 = No acknowledge signal response is sent (i.e., acknowledge bit
= 1)
0 = An acknowledge signal will be sent out to the bus at the 9th
clock bit after receiving one byte data
RSTA — Repeat Start
Writing a 1 to this bit will generate a repeated START condition on the
bus, provided it is the current bus master. This bit will always be read
as a low. Attempting a repeated start at the wrong time, if the bus is
owned by another master, will result in loss of arbitration.
1 = Generate repeat start cycle
RESERVED
Bit 1 of the IBCR is reserved for future compatibility. This bit will
always read 0.
IBSWAI — I-Bus Interface Stop in WAIT mode
1 = Halt IIC Bus module clock generation in WAIT mode
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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