Datasheet

Inter-IC Bus (IIC)
Register Descriptions
MC9S12DP256 — Revision 1.1
Inter-IC Bus (IIC)
IIC Control
Register (IBCR)
Read and write anytime
IBEN — I-Bus Enable
This bit controls the software reset of the entire IIC Bus module.
1 = The IIC Bus module is enabled. This bit must be set before any
other IBCR bits have any effect.
0 = The module is reset and disabled. This is the power-on reset
situation. When low the interface is held in reset but registers
can still be accessed.
If the IIC Bus module is enabled in the middle of a byte transfer the
interface behaves as follows: slave mode ignores the current transfer
on the bus and starts operating whenever a subsequent start
condition is detected. Master mode will not be aware that the bus is
busy, hence if a start cycle is initiated then the current bus cycle may
become corrupt. This would ultimately result in either the current bus
master or the IIC Bus module losing arbitration, after which bus
operation would return to normal.
IBIE — I-Bus Interrupt Enable
1 = Interrupts from the IIC Bus module are enabled. An IIC Bus
interrupt occurs provided the IBIF bit in the status register is
also set.
0 = Interrupts from the IIC Bus module are disabled. Note that this
does not clear any currently pending interrupt condition.
MS/SL
— Master/Slave mode select bit
Upon reset, this bit is cleared. When this bit is changed from 0 to 1, a
START signal is generated on the bus, and the master mode is
selected. When this bit is changed from 1 to 0, a STOP signal is
Address Offset: $0002
Bit 7 654321Bit 0
IBEN IBIE MS/SL
Tx/Rx TXAK RSTA 0 IBSWAI
Reset:
00000000
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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