Datasheet

Inter-IC Bus (IIC)
MC9S12DP256 — Revision 1.1
Inter-IC Bus (IIC)
The number of clocks from the falling edge of SCL to the first tap
(Tap[1]) is defined by the values shown in the scl2tap column of
Figure 84, all subsequent tap points are separated by 2
IBC5-3
as
shown in the tap2tap column in Figure 84. The SCL Tap is used to
generated the SCL period and the SDA Tap is used to determine the
delay from the falling edge of SCL to SDA changing, the SDA hold
time.
IBC7–6 defines the divider factor DIV. The values of DIV are shown
in Table 85.
The equation used to generate the divider values from the IBFD bits
is:
The SDA hold delay is equal to the CPU clock period multiplied by the
SDA Hold value shown in Table 1-2. The equation used to generate
the SDA Hold value from the IBFD bits is:
111 126 128
Table 85 Divider Factor
IBC7-6 DIV
00 1
01 2
10 4
11 RESERVED
IBC5-3
(bin)
scl2tap
(clocks)
tap2tap
(clocks)
SCL Divider DIV 2 scl2tap SCL_Tap 1–()tap2tap×[]2++()×{}×=
SCL Hold DIV scl2tap SCL_Tap 1–()tap2tap×[]3++{}×=
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