Datasheet

Inter-IC Bus (IIC)
Register Descriptions
MC9S12DP256 — Revision 1.1
Inter-IC Bus (IIC)
IIC Frequency
Divider Register
(IBFD)
Read and write anytime
IBC7–IBC0 — I-Bus Clock Rate 7–0
This field is used to prescale the clock for bit rate selection. The bit
clock generator is implemented as a prescale divider: IBC7–6 and
IBC5–3 select the prescaler divider, and IBC2–0 select the shift
register tap point. The IBC bits are decoded to give the Tap and
Prescale values as shown in Table 84.
Address Offset: $0001
Bit 7 654321Bit 0
IBC7 IBC6 IBC5 IBC4 IBC3 IBC2 IBC1 IBC0
Reset:
00000000
Table 84 I-Bus Tap and Prescale Values
IBC2-0
(bin)
SCL Tap
(clocks)
SDA Tap
(clocks)
000 5 1
001 6 1
010 7 2
011 8 2
100 9 3
101 10 3
110 12 4
111 15 4
IBC5-3
(bin)
scl2tap
(clocks)
tap2tap
(clocks)
000 5 1
001 6 2
010 6 4
011 6 8
100 14 16
101 30 32
110 62 64
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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