Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates
Inter-IC Bus (IIC)
MC9S12DP256 — Revision 1.1
Inter-IC Bus (IIC)
IIC Address
Register (IBAD)
Read and write anytime
This register contains the address the IIC Bus will respond to when
addressed as a slave; note that it is not the address sent on the bus
during the address transfer
ADR7–ADR1 — Slave Address
Bit 1 to bit 7 contain the specific slave address to be used by the IIC
Bus module.
The default mode of IIC Bus is slave mode for an address match on
the bus.
RESERVED
Bit 0 of the IBAD is reserved for future compatibility. This bit will
always read 0.
Address Offset: $0000
Bit 7 654321Bit 0
ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 0
RESET: 00000000
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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