Datasheet

Inter-IC Bus (IIC)
MC9S12DP256 — Revision 1.1
Inter-IC Bus (IIC)
iic_sda_obe If the pad is controlled by the IIC, then this signal determines whether the
IIC will drive iic_sda_do.
Interrupt Signals The IIC has one interrupt signal iic_int. Refer to Section 6 of this
document for the details regarding this signal.
Module Memory Map
The memory map for the IIC module is given below in Table 3-1. The
Address listed for each register is the address offset. The total address
for each register is the sum of the base address for the IIC module and
the address offset for each register.
Table 82 Module Memory Map
Offset Use Access
$0000 IIC Address Register Read/Write
$0001 IIC Frequency Divider Register Read/Write
$0002 IIC Control Register Read/Write
$0003 IIC Status Register) Read/Write
$0004 IIC Data I/O Register Read/Write
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