Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates
Inter-IC Bus (IIC)
Block Diagram
MC9S12DP256 — Revision 1.1
Inter-IC Bus (IIC)
• Wait Mode
IIC operation in wait mode is a configurable low power mode.
Depending on the state of internal bits, the IIC can operate
normally when the CPU is in wait mode or the IIC clock generation
can be turned off and the IIC module enters a power conservation
state during wait mode. In the later case, any transmission or
reception in progress stops at wait mode entry.
• Stop Mode
The IIC is inactive in stop mode for reduced power consumption.
The STOP instruction does not affect IIC register states.
Block Diagram
The block diagram of the IIC module is shown in Figure 87.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...