Datasheet

Serial Peripheral Interface (SPI)
Interrupts
MC9S12DP256 — Revision 1.1
Serial Peripheral Interface (SPI)
Description of
Interrupt
Operation
The Serial Peripheral Interface only originates interrupt requests. The
following is a description of how the Serial Peripheral Interface makes a
request and how the MCU should acknowledge that request. The
interrupt vector offset and interrupt priority are chip dependent.
MODF Description MODF occurs when the master detects an error on the SS
pin. The
master SPI must be configured for the MODF feature (see Table 76).
Once MODF is set, the current transfer is halted and the following bits
are changed:
• SPE=0, The SPI automatically disables itself.
• MSTR=0, The master bit in SPICR1 resets.
The MODF interrupt is reflected in the status register MODF flag.
Clearing the flag will also clear the interrupt. This interrupt will stay active
while the MODF flag is set. MODF has an automatic clearing process
which is described in SPI Status Register (SPISR).
SPIF Description SPIF occurs when the SPI receives/transmits the last SCK edge in a
data transfer operation. Once SPIF is set, it does not clear until it is
serviced. SPIF has an automatic clearing process which is described in
SPI Status Register (SPISR). In the event that the SPIF is not serviced
before the end of the next transfer (i.e. SPIF remains active throughout
another transfer), the latter transfers will be ignored and no new data will
be copied into the SPIDR.
SPTEF Description SPTEF occurs when the SPI Data register transfers a byte into the
transmit buffer Once SPTEF is set, it does not clear until it is serviced.
SPTEF has an automatic clearing process which is described in SPI
Status Register (SPISR).
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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