Datasheet

Serial Peripheral Interface (SPI)
MC9S12DP256 — Revision 1.1
Serial Peripheral Interface (SPI)
This hazard is most visible when the SCK runs at div2 of the slave’s
module clock. At other baud rates, there is more time between the falling
SS signal and the first SCK edge. i.e. div4 has two module clocks
between the SS fall and the SCK edge.
Reset
The reset values of registers and signals are described in Registers. All
registers reset to a particular value. If a data transmission occurs in slave
mode after reset without a write to SPIDR, it will transmit random data or
the byte last received from the master before the reset. Reading from the
SPIDR after reset will always read a byte of zeros.
Interrupts
This section describes interrupts originated by the Serial Peripheral
Interface. The MCU must service the interrupt requests. Table 80 lists
the three sources of interrupts generated by the SPI module. The SPI
module communicates with the MCU through one interrupt port.
Table 80 SPI Interrupt Signals
Interrupt
sources
(1)
Offset Vector Priority
Interrupt
Port
Description
Mode Fault
Chip
Dependent
Chip
Dependent
Chip
Dependent
spi_int
Active high detect. MODF occurs when a
logic zero occurs on the SS
pin of a master
SPI
Transfer Complete
Chip
Dependent
Chip
Dependent
Chip
Dependent
spi_int
Active high detect. SPIF occurs after the
last SCK cycle in a data transfer operation
to indicate that the transfer is complete.
SPI Transmitter
Empty
Chip
Dependent
Chip
Dependent
Chip
Dependent
spi_int
Active high detect. SPTEF occurs when
the SPI data register transfers a byte into
the Transmit shift register.
1. SPI Interrupts must be enabled by setting the SPIE bit or SPTIE bit in the SPICR1. Otherwise, *_int signal will never toggle
to high.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...