Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Pinout and Signal Description
MC9S12DP256 — Revision 1.1
Pinout and Signal Description
Table 6 MC9S12DP256 Power and Ground Connection Summary
Mnemonic
Pin Number
Nominal
Voltage
Description
112-pin QFP
V
DD1, 2
13, 65 2.5 V
Internal power and ground generated by internal regulator
V
SS1, 2
14, 66 0V
V
DDR
41 5.0 V
External power and ground, supply to pin drivers and internal
voltage regulator.
V
SSR
40 0 V
V
DDX
107 5.0 V
External power and ground, supply to pin drivers.
V
SSX
106 0 V
V
DDA
83 5.0 V Operating voltage and ground for the analog-to-digital
converters and the reference for the internal voltage regulator,
allows the supply voltage to the A/D to be bypassed
independently.
V
SSA
86 0 V
V
RL
85 0 V
Reference voltages for the analog-to-digital converter.
V
RH
84 5.0 V
V
DDPLL
43 2.5 V Provides operating voltage and ground for the Phased-Locked
Loop. This allows the supply voltage to the PLL to be
bypassed independently. Internal power and ground
generated by internal regulator.
V
SSPLL
45 0 V
VREGEN 97 5V Internal Voltage Regulator enable/disable
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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