Datasheet

Serial Peripheral Interface (SPI)
Errata
MC9S12DP256 — Revision 1.1
Serial Peripheral Interface (SPI)
Errata
There is a case where data may be lost between the master and slave
SPI modules. This occurs only if the following settings are true:
1. SCK is running at busclock/2 in slave mode of operation
2. Transmission protocol CPHA = 0
3. SPIDR write to slave just before SS sync goes low
Figure 86 depicts the module clock just before the SCK edge. Since the
SPTEF flag is high a write to the SPIDR is allowed in cycle shown in the
figure.
This write results in a load of the shifter, which in turn causes the MISO
to change. The changing MISO happens at about the time when the
master wishes to sample the MISO line. The first bit of the transfer may
not be stable when the master samples it, so the byte sent to the master
may be corrupted.
Figure 86 Data Transfer Error
SCK (CPOL = 0)
SAMPLE I
CHANGE O
SCK (CPOL = 1)
CHANGE O
SEL SS
(I)
MOSI pin
MISO pin
MOSI/MISO
Module Clock
Actual MISO pin
Load data to shifter
SPIDR write in this cycle
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...