Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates
Serial Peripheral Interface (SPI)
MC9S12DP256 — Revision 1.1
Serial Peripheral Interface (SPI)
– If SPISWAI is set and the SPI is configured for master, any
transmission and reception in progress stops at wait mode
entry. The transmission and reception resumes when the SPI
exits wait mode.
– If SPISWAI is set and the SPI is configured as a slave, any
transmission and reception in progress continues if the SCK
continues to be driven from the master. This keeps the slave
synchronized to the master and the SCK.
If the master transmits several bytes while the slave is in wait
mode, the slave will continue to send out bytes consistent with
the its operation mode at the start of wait mode (i.e. If the slave
is currently sending its SPIDR to the master, it will continue to
send the same byte. Else if the slave is currently sending the
last received byte from the master, it will continue to send each
previous master byte).
NOTE:
Care must be taken when expecting data from a master while the slave
is in wait or stop mode. Even though the shift register will continue to
operate, the rest of the SPI is shut down (i.e. a SPIF interrupt will not be
generated until exiting stop or wait mode). Also, the byte from the shift
register will not be copied into the SPIDR register until after the slave SPI
has exited wait or stop mode. A SPIF flag and SPIDR copy is only
generated if wait mode is entered or exited during a tranmission. If the
slave enters wait mode in idle mode and exits wait mode in idle mode,
neither a SPIF nor a SPIDR copy will occur.
SPI in Stop Mode Stop mode is dependent on the system. The SPI enters stop mode when
the module clock is disabled (held high or low). If the SPI is in master
mode and exchanging data when the CPU enters stop mode, the
transmission is frozen until the CPU exits stop mode. After stop, data to
and from the external SPI is exchanged correctly. In slave mode, the SPI
will stay synchronized with the master.
The stop mode is equivalent to the wait mode with the SPISWAI bit set
except that the stop mode is not dependent on the SPISWAI bit.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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