Datasheet

Serial Peripheral Interface (SPI)
Low Power Mode Options
MC9S12DP256 — Revision 1.1
Serial Peripheral Interface (SPI)
In the special case where the MODFEN bit is cleared, the SS pin is a
general purpose input/output pin for the SPI system configured in master
mode. In this special case, the mode error function is inhibited and
MODF remains cleared.
In case the SPI system is configured as a slave and the MODFEN bit is
cleared the SS
pin is a dedicated input pin.
When a mode fault error occurs, the SPE and MSTR bits are cleared
thereby clearing the output enable for the SCK, MISO, and MOSI (for
MOMI) pins cleared. This forces those pins to be high impedance inputs
to avoid any possibility of conflict with another output driver.
If the mode fault error occurs in the bidirectional mode for a SPI system
configured in master mode, MISO (SISO) is not affected. No mode fault
error occurs in the bidirectional mode for SPI system configured in slave
mode.
The mode fault flag is cleared automatically by a read of the SPI status
register (with MODF set) followed by a write to SPI control register 1.
Low Power Mode Options
SPI in Run Mode In run mode with the SPI system enable (SPE) bit in the SPI control
register clear, the SPI system is in a low-power, disabled state. SPI
registers can still be accessed, but clocks to the core of this module are
disabled.
SPI in Wait Mode SPI operation in wait mode depends upon the state of the SPISWAI bit
in SPI control register 2.
• If SPISWAI is clear, the SPI operates normally when the CPU is in
wait mode
• If SPISWAI is set, SPI clock generation ceases and the SPI
module enters a power conservation state when the CPU is in wait
mode.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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