Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Serial Peripheral Interface (SPI)
Functional Description
MC9S12DP256 — Revision 1.1
Serial Peripheral Interface (SPI)
Special Features
SS
Output The SS output feature automatically drives the SS pin low during
transmission to select external devices and drives it high during idle to
deselect external devices. When SS
output is selected, the SS output
pin is connected to the SS
input pin of the external device.
The SS
output is available only in master mode during normal SPI
operation by asserting SSOE and MODFEN bit as shown in Table 76.
The mode fault feature is disabled while SS output is enabled.
NOTE:
Care must be taken when using the SS output feature in a multimaster
system since the mode fault feature is not available for detecting system
errors between masters.
Bidirectional
Mode (MOMI or
SISO)
The bidirectional mode is selected when the SPC0 bit is set in SPI
control register 2 (see Normal Mode and Bidirectional Mode). In this
mode, the SPI uses only one serial data pin for the interface with external
device(s). The MSTR bit decides which pin to use. The MOSI pin
becomes the serial data I/O (MOMI) pin for the master mode, and the
MISO pin becomes serial data I/O (SISO) pin for the slave mode. The
MISO pin in the master mode and MOSI pin in the slave mode become
general-purpose I/O.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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