Datasheet

Serial Peripheral Interface (SPI)
MC9S12DP256 — Revision 1.1
Serial Peripheral Interface (SPI)
automatically when the SPI status register is read (with SPIF set)
followed by a read or write to the SPI data register. If the SPIE bit is set
when the SPIF flag is set, a hardware interrupt is requested.
SPI Baud Rate
Generation
Baud rate generation consists of a series of divider stages. Six bits in the
SPI baud rate register (SPPR2, SPPR1, SPPR0, SPR2, SPR1, and
SPR0) determine the divisor to the SPI module clock which results in the
SPI baud rate.
The SPI clock rate is determined by the product of the value in the baud
rate preselection bits (SPPR2–SPPR0) and the value in the baud rate
selection bits (SPR2–SPR0). The module clock divisor equation is
shown in Figure 85.
When all bits are clear (the default condition), the SPI module clock is
divided by 2. When the selection bits (SPR2–SPR0) are 001 and the
preselection bits (SPPR2–SPPR0) are 000, the module clock divisor
becomes 4. When the selection bits are 010, the module clock divisor
becomes 8, etc.
When the preselection bits are 001, the divisor determined by the
selection bits is multiplied by 2. When the preselection bits are 010, the
divisor is multiplied by 3, etc. See Table 78 for baud rate calculations for
all bit conditions, based on a 25 MHz SPI module clock.The two sets of
selects allows the clock to be divided by a non-power of two to achieve
other baud rates such as divide by 6, divide by 10, etc.
The baud rate generator is activated only when the SPI is in the master
mode and a serial transfer is taking place. In the other cases, the divider
is disabled to decrease I
DD
current.
Figure 85 Baud Rate Divisor Equation
BaudRateDivisor SPPR 1+()2•
SPR 1+()
=
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