Datasheet

Serial Peripheral Interface (SPI)
Functional Description
MC9S12DP256 — Revision 1.1
Serial Peripheral Interface (SPI)
and MOSI pins are connected directly between the master and the slave.
The MISO signal is the output from the slave, and the MOSI signal is the
output from the master. The SS
line is the slave select input to the slave.
The SS
pin of the master must be either high or reconfigured as a
general-purpose output not affecting the SPI.
Figure 84 SPI Clock Format 1 (CPHA = 1)
The SS
line can remain active low between successive transfers (can be
tied low at all times). This format is sometimes preferred in systems
having a single fixed master and a single slave that drive the MISO data
line.
The SPI interrupt request flag (SPIF) is common to both the master and
slave modes. SPIF gets set after the last SCK cycle in a data transfer
operation to indicate that the transfer is complete. SPIF is cleared
t
L
t
T
for t
T
, t
l
, t
L
Minimum 1/2 SCK
t
I
t
L
If next transfer begins here
Begin End
SCK (CPOL = 0)
SAMPLE I
CHANGE O
SEL SS (O)
Transfer
SCK (CPOL = 1)
MSB first (LSBFE = 0):
LSB first (LSBFE = 1):
MSB
LSB
LSB
MSB
Bit 5
Bit 2
Bit 6
Bit 1
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
CHANGE O
SEL SS (I)
MOSI pin
MISO pin
Master only
MOSI/MISO
t
L
= Minimum leading time before the first SCK edge
t
T
= Minimum trailing time after the last SCK edge
t
I
= Minimum idling time between transfers (minimum SS high time)
t
L
, t
T
, and t
I
are guaranteed for the master mode and required for the slave mode.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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