Datasheet

Serial Peripheral Interface (SPI)
MC9S12DP256 — Revision 1.1
Serial Peripheral Interface (SPI)
The SS line can remain active low between successive transfers.
NOTE: There is a functional hazard, the SPI may lose data in this mode
(CPHA=0) if configured as a slave with the SCK rate at div2 of the
slave’s module clock (see Errata).
CPHA = 1 Transfer
Format
Some peripherals require the first SCK edge before the first data bit
becomes available at the data out pin; the second edge clocks data into
the system. In this format, the first SCK edge is issued by setting the
CPHA bit at the beginning of the 8-cycle transfer operation.
The first edge of SCK occurs immediately after the half SCK clock cycle
synchronization delay. This first edge commands the slave to transfer its
most significant data bit to the serial data input pin of the master.
A half SCK cycle later, the second edge appears on the SCK pin. This is
the latching edge for both the master and slave.
When the third edge occurs, the value previously latched from the serial
data input pin is shifted into the LSB of the SPI shifter. After this edge,
the next bit of the master data is coupled out of the serial data output pin
of the master to the serial input pins on the slave.
This process continues for a total of 16 edges on the SCK line with data
being latched on even numbered edges and shifting taking place on odd
numbered edges.
Data reception is double buffered; data is serially shifted into the SPI
shift register during the transfer and is transferred to the parallel SPI data
register after the last bit is shifted in.
After the 16th SCK edge:
• Data that was previously in the SPI data register of the master is
now in the data register of the slave, and data that was in the data
register of the slave is in the master.
• The SPIF flag bit in SPISR is set indicating that the transfer is
complete.
Figure 84 shows two clocking variations for CPHA = 1. The diagram may
be interpreted as a master or slave timing diagram since the SCK, MISO,
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