Datasheet

Serial Peripheral Interface (SPI)
Functional Description
MC9S12DP256 — Revision 1.1
Serial Peripheral Interface (SPI)
Even numbered edges cause the value previously latched from the
serial data input pin to shift into the LSB of the SPI shifter.
If the CPHA bit is set, even numbered edges on the SCK input cause the
data at the serial data input pin to be latched. Odd numbered edges
cause the value previously latched from the serial data input pin to shift
into the LSB of the SPI shifter.
When CPHA is set, the first edge is used to get the first data bit onto the
serial data output pin. When CPHA is clear and the SS
input is low (slave
selected), the first bit of the SPI data is driven out of the serial data output
pin. After the eighth shift, the transfer is considered complete and the
received data is transferred into the SPI data register. To indicate
transfer is complete, the SPIF flag in the SPI status register is set.
Transmission
Formats
During an SPI transmission, data is transmitted (shifted out serially) and
received (shifted in serially) simultaneously. The serial clock (SCK)
synchronizes shifting and sampling of the information on the two serial
data lines. A slave select line allows selection of an individual slave SPI
device; slave devices that are not selected do not interfere with SPI bus
activities. Optionally, on a master SPI device, the slave select line can
be used to indicate multiple-master bus contention.
Figure 82 Master/Slave Transfer Block Diagram
SHIFT REGISTER
SHIFT REGISTER
BAUD RATE
GENERATOR
MASTER SPI SLAVE SPI
V
DD
MOSI MOSI
MISO MISO
SCK SCK
SS
SS
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Freescale Semiconductor, Inc.
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