Datasheet

Serial Peripheral Interface (SPI)
MC9S12DP256 — Revision 1.1
Serial Peripheral Interface (SPI)
status register. If the SPI interrupt enable bit (SPIE) is set when the
MODF bit gets set, then an SPI interrupt sequence is also requested
When a write to the SPI data register in the master occurs, there is a half
SCK-cycle delay. After the delay, SCK is started within the master. The
rest of the transfer operation differs slightly, depending on the clock
format specified by the SPI clock phase bit, CPHA, in SPI control register
1 (see Transmission Formats).
Slave Mode The SPI operates in slave mode when the MSTR bit in SPI control
register1 is clear. In slave mode, SCK is the SPI clock input from the
master, and SS
is the slave select input. Before a data transmission
occurs, the SS
pin of the slave SPI must be at logic 0. SS must remain
low until the transmission is complete.
In slave mode, the function of the serial data output pin (MISO) and serial
data input pin (MOSI) is determined by the SPC0 bit in SPI control
register 2 and the MSTR control bit. While in slave mode, the SS
input
controls the serial data output pin; if SS
is high (not selected), the serial
data output pin is high impedance, and, if SS
is low the first bit in the SPI
data register is driven out of the serial data output pin. Also, if the slave
is not selected (SS
is high), then the SCK input is ignored and no internal
shifting of the SPI shift register takes place.
Although the SPI is capable of full-duplex operation, some SPI
peripherals are capable of only receiving SPI data in a slave mode. For
these simpler devices, there is no serial data out pin.
NOTE: When peripherals with full-duplex capability are used, take care not to
simultaneously enable two receivers whose serial outputs drive the
same system slave’s serial data output line.
As long as no more than one slave device drives the system slave’s
serial data output line, it is possible for several slaves to receive the
same transmission from a master, although the master would not
receive return information from all of the receiving slaves.
If the CPHA bit in SPI control register 1 is clear, odd numbered edges on
the SCK input cause the data at the serial data input pin to be latched.
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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