Datasheet

Serial Peripheral Interface (SPI)
Functional Description
MC9S12DP256 — Revision 1.1
Serial Peripheral Interface (SPI)
two fundamentally different protocols by shifting the clock by a half cycle
or by not shifting the clock (see Transmission Formats).
The SPI can be configured to operate as a master or as a slave. When
MSTR in SPI control register1 is set, the master mode is selected; when
the MSTR bit is clear, the slave mode is selected.
Master Mode The SPI operates in master mode when the MSTR bit is set. Only a
master SPI module can initiate transmissions. A transmission begins by
writing to the master SPI data register. If the shift register is empty, the
byte immediately transfers to the shift register. The byte begins shifting
out on the MOSI pin under the control of the serial clock.
The SPR2, SPR1, and SPR0 baud rate selection bits in conjunction with
the SPPR2, SPPR1, and SPPR0 baud rate preselection bits in the SPI
baud rate register control the baud rate generator and determine the
speed of the shift register. The SCK pin is the SPI clock output. Through
the SCK pin, the baud rate generator of the master controls the shift
register of the slave peripheral.
Consecutive transmissions are possible but care should be taken to set
the Baud rate selection bits to correspond to a frequency less than
busclock/4.
In master mode, the function of the serial data output pin (MOSI) and the
serial data input pin (MISO) is determined by the SPC0 and MSTR
control bits.
The SS
pin is normally an input which should remain in the inactive high
state. However, in the master mode, if both MODFEN bit and SSOE bit
are set, then the SS
pin is the slave select output.
The SS
output becomes low during each transmission and is high when
the SPI is in the idling state. If the SS
input becomes low while the SPI
is configured as a master, it indicates a mode fault error where more than
one master may be trying to drive the MOSI and SCK lines
simultaneously. In this case, the SPI immediately clears the output buffer
enables associated with the MISO, MOSI (or MOMI), and SCK pins so
that these pins become inputs. This mode fault error also clears the SPE
and MSTR control bits and sets the mode fault (MODF) flag in the SPI
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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