Datasheet
Table Of Contents
- List of Sections
- Table of Contents
- General Description
- Central Processing Unit (CPU)
- Pinout and Signal Description
- System Configuration
- Registers
- Operating Modes
- Resource Mapping
- Bus Control and Input/Output
- Resets and Interrupts
- Voltage Regulator (VREG)
- Flash EEPROM 256K
- EEPROM 4K
- Port Integration Module
- Clocks and Reset Generator (CRG)
- Pulse Width Modulator (PWM)
- Enhanced Capture Timer (ECT)
- Serial Communications Interface (SCI)
- Serial Peripheral Interface (SPI)
- Inter-IC Bus (IIC)
- MSCAN
- Analog to Digital Converter
- Byte Data Link Controller Module
- Contents
- Overview
- Features
- Block Diagram
- Register Map
- Functional Description
- Register Descriptions
- External Pin Descriptions
- Reset Initialization/Basic Operation
- Transmitting A Message
- Receiving A Message
- Transmitting An In-Frame Response (IFR)
- Receiving An In-Frame Response (IFR)
- Special BDLC Operations
- Modes of Operation
- Interrupt Operation
- Low Power Options
- Background Debug Module (BDM)
- Breakpoint (BKP) Module
- Revision History
- Glossary
- Literature Updates

Serial Peripheral Interface (SPI)
MC9S12DP256 — Revision 1.1
Serial Peripheral Interface (SPI)
Functional Description
The SPI module allows full-duplex, synchronous, serial communication
between the MCU and peripheral devices. Software can poll the SPI
status flags or SPI operation can be interrupt driven.
The SPI system is enabled by setting the SPI enable (SPE) bit in SPI
control register 1. While SPE is set, the four associated SPI port pins are
dedicated to the SPI function as:
• Slave select (SS
)
• Serial clock (SCK)
• Master out/slave in (MOSI)
• Master in/slave out (MISO)
The main element of the SPI system is the SPI data register. The 8-bit
data register in the master and the 8-bit data register in the slave are
linked by the MOSI and MISO pins to form a distributed 16-bit register.
When a data transfer operation is performed, this 16-bit register is
serially shifted eight bit positions by the SCK clock from the master; data
is exchanged between the master and the slave. Data written to the
master SPI data register becomes the output data for the slave, and data
read from the master SPI data register after a transfer operation is the
input data from the slave.
A write to the SPI data register puts data into the transmit buffer if the
previous transmission was complete. When a transfer is complete,
received data is moved into a receive data register. Data may be read
from this double-buffered system any time before the next transfer is
complete. This 8-bit data register acts as the SPI receive data register
for reads and as the SPI transmit data register for writes. A single SPI
register address is used for reading data from the read data buffer and
for writing data to the shifter.
The clock phase control bit (CPHA) and a clock polarity control bit
(CPOL) in the SPI control register 1 select one of four possible clock
formats to be used by the SPI system. The CPOL bit simply selects a
non-inverted or inverted clock. The CPHA bit is used to accommodate
Freescale Semiconductor, I
Freescale Semiconductor, Inc.
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